Citation link:
Authors:
Chumachenko, Vasiliy Platonovich; Vasileva, Tanichka Krumova; Чумаченко, Василий Платонович; Василева, Таничка Крумова
Title:
Gate delay model of pass - transistor logic
Other Titles:
Модел на закъснението на логически елементи с трансмисионни транзистори
Date of Issue:
1995
Is Part of:
Годишник на ТУ-София, 48(4), 1995, Електроника, комуникации, информатика, автоматика : Юбилейна научна сесия „50 години ТУ–София“ 11-12.10.1995 София, с. 63-72.
Publisher:
ТУ-София
Identifiers:
0374-342X [issn]
Type:
Article
Language:
eng
Subject:
транзистори – моделиране; transistors - modeling
Abstract:
A simple gate delay model useful for analysis and optimization of pass-transistor logic circuit is proposed. The macromodel is based on device equation and is found to be an analytical function of capacitive. load and device sizes. Curve fitting of model equation to SPICE simulation results is used for coefficient obtaining. The procedure for coefficient extracting is technology-independent. Once obtained they can be applied to any design with the same device technology. The model is precise and applicable to delay prediction of broad class of circuits containing combination of pass transistors and inverters.
Description:
Chumachenko, Vassiliy Platonovich et al. Gate delay model of pass - transistor logic / Vassiliy Tchoumatchenko, Tania Vassileva. (Electronics). // Годишник на ТУ-София, Том 48, 1995, № 4. Електроника, комуникации, информатика, автоматика : Юбилейна научна сесия „50 години ТУ–София“ 11-12.10.1995 София, с. 63-72 : със сх., формули, диагр. - Рез. на бълг. и англ. ез.; С библиогр.
