Citation link:
Authors:
Vasileva, Tanichka Krumova; Василева, Таничка Крумова; Tchumatchenko, Vasiliy Platonovich; Чумаченко, Платонович Василий
Title:
Multiplier design migration from FPGA to standard cell technology
Other Titles:
Миграция на проект на умножител от технология с FPGA схеми към стандартни клетки
Date of Issue:
1995
Is Part of:
Годишник на ТУ-София, 48(4). Електроника, комуникации, информатика, автоматика : Юбилейна научна сесия „50 години ТУ–София“ 11-12.10.1995 София, с. 19-28.
Publisher:
ТУ-София
Identifiers:
0374-342X [issn]
Type:
Article
Language:
bul
Subject:
интегрални схеми – технология; integrated circuits - technology
Abstract:
Standard Cell implementation of an 0(n) parallel multiplier with bit-sequential input and output, using Field Programmable Gate Arrays (FPGA) design as a prototype is considered. Problems facing in design migration from FPGA to standard cells design approach are discussed. Applying logic circuit optimization as a manner to improve design performances in terms of speed and die size (and•. therefore silicon costs) is also outlined. The benefits are an decreased number of cells used (within 44%) as well as reducing of core area with 43% compared to non-optimized version.
Description:
Vasileva, Tanichka Krumova et al. Multiplier design migration from FPGA to standard cell technology / T. Vassileva, V. Tchumatchenko. (Electronics). // Годишник на ТУ-София, Том 48, 1995, № 4. Електроника, комуникации, информатика, автоматика : Юбилейна научна сесия „50 години ТУ–София“ 11-12.10.1995 София, с. 19-28 : с, табл., сх., диагр., ил. - Рез. на бълг. и англ. ез.; С библиогр.
